1. Field of the Invention
The invention generally relates to a semiconductor device, and more particularly, to a wire structure including a bit line and a method for manufacturing the same.
2. Brief Description of Related Technology
In order to increase an integration degree of a semiconductor device, various modification on a cell layout have been attempted to integrate more circuit patterns within a limited area of a wafer or a semiconductor substrate. In a Dynamic Random Access Memory (DRAM) device, there have been attempted changes on an arrangement of active regions, on which transistor devices are formed, from 8F2 cell layout into 6F2 cell layout.
The DRAM device is configured so that word lines and bit lines are arranged perpendicular to each other. In the 8F2 cell layout, rectangular active regions, major axes of which are extended in a direction perpendicular to the word line, are repeatedly arranged. However, in the 6F2 cell layout, active regions, major axes of which are extended in a direction diagonally intersecting with the word line, are repeatedly arranged. Therefore, a distance between adjacent bit lines is decreased as compared to that of the 8F2 cell layout and a memory cell can be formed within a smaller area.
FIGS. 1 and 2 are a plan view and a cross-sectional view illustrating bit lines in the 6 F2 cell layout.
Referring to FIG. 1, an isolation region 15 that delimits an active region 11 in a diagonal pattern is formed on a semiconductor substrate 10 in a Shallow Trench Isolation (STI) structure. The active region 11 in the diagonal pattern is arranged in a pattern extending in a diagonal direction that intersects a bit line 30 at a non-right angle, for example, an angle of about 27°. In this active region 11, a word line including a gate that diagonally intersects the active region 11 at an angle of about 63° is formed to thereby configure a transistor structure (not shown). Also, the bit line 30 is arranged so as to be electrically connected to the active region 11 through a bit line contact 20.
A memory cell of a DRAM device includes one transistor and one capacitor (not shown), and the capacitor is stacked above the bit line 30. In an under layer of the bit line contact 20, as shown in FIG. 2, a first insulation layer 41 insulating the semiconductor substrate 10 from the bit line 30 is introduced and a storage node contact pad 51 to be electrically connected to a storage node or a lower electrode and a bit line contact pad 55 to be electrically connected to the bit line 30 are introduced penetrating the first insulation layer 41. The bit line contact 20 is formed so as to penetrate a second insulation layer 43, and a third insulation layer 45 is introduced so as to cover the bit line 30.
The storage node is formed above the bit line 30 and a storage node contact 61 to connect this storage node and the storage node contact pad 51 is penetratingly formed between the bit lines 30. Because, a first distance D1 between adjacent bit lines 30 is very narrow due to reductions in the design rule, a contact hole for the bit line contact 61 can be formed as a Self Aligned Contact (SAC). As the storage node contact 61 is formed in the SAC process, a capping layer 37 above the bit line 30 and spacers 39 attached to side walls of the bit line 30 act as etch barriers that resist against the etch, upon formation of the storage node contact hole.
In order that the storage node contact 61 and the bit line contact 20 are insulated from each other, a second portion 35 of the bit line 30, overlapping the bit line contact 20, is designed to have a Critical Dimension (CD) wider than that of a linear-shaped first portion 31 of the bit line 30. That is to say, the second portion 35 of the bit line 30 is designed to have a wider CD so that the storage node contact 61 and the bit line contact 20 have a second distance D2. Therefore, a planar layout of the bit line is designed as a dog bone-shape in which the second portion 35 has a wider CD and the first portion 31 has a narrower CD as shown in FIG. 1.
In order to ensure the larger first distance D1 between adjacent bit lines 30, the first portion 31 of the bit line 30 is designed to have a narrow CD. This is for restricting signal interference between adjacent bit lines 30 and inducing more stable gap filling of the third insulation layer 45, which is formed to fill between the bit lines 30, as the design rule is decreased to 40 nanometers (nm) scale. However, as the bit line 30 is designed to have a dog bone-shape as described above, it becomes more difficult to transfer the bit line 30 onto the semiconductor substrate 10 by a photolithography process. That is to say, because the bit line 30 is designed in a dog bone-shape having the second portion 35 with larger CD, it becomes quite difficult to accurately transfer this dog bone-shape onto the semiconductor substrate 10. Therefore, it is difficult to ensure a process margin for patterning of the bit line 30 in this dog bone-shape and a short between the bit lines 30 may result therefrom after an etch process.
Because it is difficult to accurately transfer the bit line 30 onto the semiconductor substrate 10 in a designed shape as the design rule is decreased to less than 40 nm, it becomes difficult to form the bit line 30 so that the first portion 31 of the bit line 30 has a desired CD. Accordingly, it becomes difficult for the capping layer 37 and the spacer 39 to act as the etch barrier in the subsequent SAC process for forming the storage node contact 61. Therefore, a short can result between the storage node contact 61 and the bit line 30, and it becomes difficult to ensure the process margin. Moreover, because an upper portion of the spacer 39 adjoining the capping layer 37 is formed having a gently curved profile, this shoulder portion can be lost in the SAC etch to expose the bit line 30.
Accordingly, it would be desirable to develop a method capable of patterning the bit line 30 with a shape more accurately corresponding to the designed shape. It would also be desirable to develop a method capable of preventing a short generated by the loss due to the SAC etch upon subsequent formation of the storage node contact.